library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Transpozycja macierzy stanu

entity data_order is
    port ( datain : in std_logic_vector (127 downto 0);
           dataout : out std_logic_vector (127 downto 0));
end data_order;

architecture Behavioral of data_order is
	alias a00 : std_logic_vector(7 downto 0) is datain(127 downto 120);
	alias a01 : std_logic_vector(7 downto 0) is datain(119 downto 112);
	alias a02 : std_logic_vector(7 downto 0) is datain(111 downto 104);
	alias a03 : std_logic_vector(7 downto 0) is datain(103 downto 96);

	alias a10 : std_logic_vector(7 downto 0) is datain(95 downto 88);
	alias a11 : std_logic_vector(7 downto 0) is datain(87 downto 80);
	alias a12 : std_logic_vector(7 downto 0) is datain(79 downto 72);
	alias a13 : std_logic_vector(7 downto 0) is datain(71 downto 64);

	alias a20 : std_logic_vector(7 downto 0) is datain(63 downto 56);
	alias a21 : std_logic_vector(7 downto 0) is datain(55 downto 48);
	alias a22 : std_logic_vector(7 downto 0) is datain(47 downto 40);
	alias a23 : std_logic_vector(7 downto 0) is datain(39 downto 32);

	alias a30 : std_logic_vector(7 downto 0) is datain(31 downto 24);
	alias a31 : std_logic_vector(7 downto 0) is datain(23 downto 16);
	alias a32 : std_logic_vector(7 downto 0) is datain(15 downto 8);
	alias a33 : std_logic_vector(7 downto 0) is datain(7 downto 0);
begin
		dataout <= a00 & a10 & a20 & a30 &
					  a01 & a11 & a21 & a31 &
					  a02 & a12 & a22 & a32 &
					  a03 & a13 & a23 & a33;
end Behavioral;

